Self-alignment techniques are used routinely in traditional MOSFET technology. The conventional technology has been called silicon gate technology. The use of III-V compounds presents different problems than those encountered in silicon technology. For example, the annealing step in the fabrication of III-V compound semiconductors generally requires a cap to prevent elemental evaporation. In the fabrication of gallium arsenide devices, caps are generally used to prevent arsine evaporation, thereby maintaining the stoichiometry of the material.
In the practice of self-alignment technology, the transistor is first fabricated up to the gate level. Ion implantation is then utilized to form highly conductive areas for the source and drain. In this ion implantation step, the gate acts as a mask to protect certain areas from ion implantation. Consequently, the highly conductive source and drain areas extend to a region directly underneath the gate area, thereby reducing source and gate resistance. Thereafter, an annealing cap is deposited and the sample is annealed for activation of the implanted species. The annealing cap is removed and further fabrication steps are implemented to produce a semiconductor device.
Controlling the gate length is extremely important in the fabrication of semiconductor devices. Circuit performance is dependent upon gate length because the transistor's performance is strongly influenced by gate length. It is highly desirable to have a slightly longer channel length underneath the gate of a semiconductor because a longer channel will reduce the breakdown voltage at the gate. It is also desirable to reduce the leakage current between the gate and the channel and to reduce the feedback (Miller effect) capacitance between the drain and the gate and the gate and the source.
Previously, a dummy gate was deposited onto a silicon dioxide layer on top of the channel region of a substrate. An aluminum layer was deposited onto the silicon dioxide before etching techniques were utilized to remove portions of the silicon dioxide layer. The resultant dummy gate was a structure of a silicon dioxide layer having an aluminum cap deposited thereon. The wafer was then ion implanted, utilizing the aluminum cap as a mask to protect the channel from ion implantation. The dummy gate was thereafter etched to form an undercut beneath the aluminum mask. This process allows the final gate metal length to be smaller than the channel length because the gate metal is deposited into the space left behind after the dummy gate has been removed.
The aluminum cap is then stripped off and an annealing cap is applied before high temperature annealing is performed, whereby arsenic evaporation is prevented in gallium arsenide devices. This method cannot reliably control the uniformity of the gate length because the undercutting operation cannot be controlled sufficiently. Additionally, the granular size of the aluminum is too large to be suitable for sub-micron geometries because a ragged gate structure is produced. Moreover, the lifting off of the aluminum gate mask after the silicon dioxide annealing cap has been deposited is difficult to achieve by using chemical etching. Because gate length strongly influence a FET's performance, circuit performance is difficult to control if gate length cannot be consistently uniform.
U.S. Pat. No. 4,532,695 issued to Schuermeyer on Aug. 6, 1985, entitled "Method of Making Self-Aligned discloses an IGFET". The IGFET is formed on a gallium arsenide wafer which is coated with a layer of silicon nitride and a silicon dioxide layer. The silicon dioxide is etched away in transistor areas and ion implanting provides channel doping. A gate of refractory metal such as molybdenum is deposited and delineated. The gate and silicon dioxide act as masks for ion implantation of the source and drain. No dummy or substitutional gates are used to control the gate length.
U.S. Pat. No. 4,472,872 issued to Toyoda, et al. on Sept. 25, 1984, entitled "Method of Fabricating a Schottky Gate Field Effect Transistor" discloses a Schottky gate FET is fabricated by forming on a semiconductor substrate first and second stacks facing each other. Each stack is constructed by an ohmic electrode and a spacer film. On the substrate having stacks formed thereon an insulation layer is formed and is anisotropically etched in the direction of its thickness until the planar surface portions are exposed. As a result, portions of the insulation layer remain on opposing sidewalls of the stacks. After removing the spacer films to define stepped portions between each remaining portion and each electrode, a layer of a metallic material capable of forming a Schottky barrier with the substrate is formed. The remaining portions are removed to pattern the metallic material layer, thereby forming a Schottky gate electrode.